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SUMMIT
MICROELECTRONICS, Inc. Distributed Power Hot-Swap Controller
SMH4812
Preliminary
FEATURES
! Soft Starts Main Power Supply on Card Insertion or System Power Up ! Senses Card Insertion via Short Pins or Ejector Switches ! Master Enable to Allow System Control of Power Up or Down " Can be used as a Temperature Sense Input ! Programmable Independent Controls of a DC/DC Converter " Not Enabled until Host Supply Fully Soft Started " Programmable Time Delay " Available Input to hold off Dependant Enables until Conditions are Satisfied ! Highly Programmable Circuit Breaker " Programmable Quick-TripTM Values " Programmable Current Limiting " Programmable Duty Cycle Times " Programmable Over-current Filter ! Programmable Host Voltage Fault Monitoring " Programmable Under-Voltage Hysteresis " Programmable UV/OV Voltage Filter " Programmable Fault Mode: Latched or Duty Cycle ! Programmable Forced Shutdown Timer ! 2.5V and 5.0V Reference Outputs " Eliminates the Need for Other Primary Voltages " Easy Expansion of External Monitor Functions ! Supply Range +20VDC to >+500VDC
SIMPLIFIED APPLICATION DRAWING
0V
Disable/Enable
VDD Pin Detect PD1#
ENPG FS#
FAULT# UV
SMH4812
OV PG2# DC/DC
Pin Detect
PD2# VSS CBSENSE VGATE 2.5VREF 5.0VREF
-48V
Characteristics subject to change without notice 2055 4.0 12/22/00
2055 SAD 1.1
(c)SUMMIT MICROELECTRONICS, Inc., 2000 * 300 Orchard City Dr., Suite 131 * Campbell, CA 95008 * Phone 408-378-3970 * FAX 408-378-6586 * www.summitmicro.com
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SMH4812
Preliminary DESCRIPTION
The SMH4812 is designed to control hot swapping of plugin cards operating from a single supply, which can have an output range from 20V to 500V. The SMH4812 hot-swap controller provides under-voltage and over-voltage monitoring of the host power supply, it drives an external power MOSFET switch that connects the supply to the load, and it protects against over-current conditions that might disrupt the host supply. When the input and output voltages to the SMH4812 controller are within specification it provides a Power Good logic output that may be used to enable a DC-DC converter. Additional features of the device include: temperature sense or master enable input, 2.5V and 5V reference outputs for expanding monitor functions, two Pin-Detect enable inputs for fault protection, and duty-cycle or latched over-current protection modes. All of these features can be programmed by the factory according to the user's requirements.
FUNCTIONAL BLOCK DIAGRAM
ENPG
14
VDD 16
12VREF
PROGRAMMABLE SHUTDOWN TIMER +
13 FS# 12 2.5VREF
DRAIN 1 SENSE
50k 50k 50k
-
11 5.0VREF
EN/TS 3 PD1# 4 PD2# 5
+ -
PROGRAMMABLE DELAY
15 PG#
UV 9
+ - FILTER +
OV 10
5V
12V
2.5V
2 VGATE
VSS 8
PROGRAMMABLE DELAY 50mV
CBSENSE 7
Programmable Quick Response Ref. Voltage
2
- 50k VGATE SENSE + - + -
6 FAULT#
DUTY CYCLE TIMER
2055 BD 3.0
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SUMMIT MICROELECTRONICS, Inc.
SMH4812
Preliminary PIN CONFIGURATION
DRAIN SENSE VGATE EN/TS PD1# PD2# FAULT# CBSENSE VSS
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VDD PG# ENPG FS# 2.5VREF 5VREF OV UV
2055 PCon 2.0
PIN DESCRIPTIONS
DRAIN SENSE (1) The DRAIN SENSE input monitors the voltage at the drain of the external power MOSFET switch with respect to VSS. An internal 10A source pulls the DRAIN SENSE signal towards the 5V reference level. DRAIN SENSE must be held below 2.5V to enable the PG outputs. EN/TS (3) The Enable/Temperature Sense input is the master enable input. If EN/TS is less than 2.5V, VGATE will be disabled. This pin has an internal 200kW pull-up to 5V. PD1#, PD2# (4, 5) These are logic level active low inputs that can optionally be employed to enable VGATE and the PG outputs when they are at VSS. These pins each have an internal 50kW pull-up to 5V. CBSENSE (7) The circuit breaker sense input is used to detect overcurrent conditions across an external, low value sense resistor (RS) tied in series with the Power MOSFET. A voltage drop of greater than 50mV across the resistor for longer than tCBD will trip the circuit breaker. A programmable Quick-Trip sense point is also available. UV (9) The UV pin is used as an under-voltage supply monitor, typically in conjunction with an external resistor ladder. VGATE will be disabled if UV is less than 2.5V. Programmable internal hysteresis is available on the UV input, adjustable in increments of 62.5mV. Also available is a filter delay on the UV input. OV (10) The OV pin is used as an over-voltage supply monitor, typically in conjunction with an external resistor ladder. VGATE will be disabled if OV is greater than 2.5V. A filter delay is available on the OV input. VGATE (2) The VGATE output activates an external power MOSFET switch. This signal supplies a constant current output (100A typical), which allows easy adjustment of the MOSFET turn on slew rate. FAULT# (6) FAULT# is an open-drain, active-low output that indicates the fault status of the device. 5VREF (11) This is a precision 5V output reference voltage that may be used to expand the logic input functions on the SMH4812. The reference output is with respect to VSS. 2.5VREF (12) This is a precision 2.5V output reference voltage that may be used to expand the logic input functions on the SMH4812. The reference output is with respect to VSS. FS# (13) The Forced Shutdown (FS#) pin is an active low input that causes VGATE and PG outputs to be shut down at any time after an internal hold-off timer has expired. The holdoff timer allows supervisory circuits on the secondary side (which are not powered up initially) to control shut down of the SMH4812 via an opto-isolator. This input has no pullup resistor.
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SMH4812
Preliminary
ENPG (14) The ENPG input controls the PG# output. When ENPG is pulled low the PG# output is immediately placed in a high impedance state. If ENPG is driven high then the PG# output will immediately be driven low. PG# (15) PG# is an open-drain, active-low output with no internal pull-up resistor. It can be used to switch a load or enable a DC/DC converter. PG# is enabled immediately after VGATE reaches VDD - VGT and the DRAIN SENSE voltage is less than 2.5V. Voltage on these pins cannot exceed 12V, as referenced to VSS.
VDD (16) VDD is the positive supply connection. An internal shunt regulator connected between VDD and VSS develops approximately 12V that supplies the SMH4812. A resistor must be placed in series with the VDD pin to limit the regulator current (RD in the application illustrations). VSS (8) VSS is connected to the negative side of the supply.
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SMH4812
Preliminary ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ...................... -55C to 125C Storage Temperature ........................... -65C to 150C Lead Solder Temperature (10 secs) ................... 300 C Terminal Voltage with Respect to VSS: VDD ................................. -0.5V to VDD OV, UV, DRAIN SENSE, FS#, CBSENSE ..... -0.5V to VDD+0.5V PD1#, PD2#, ENPG, EN/TS ......... 10V FAULT#, PG# ........ -0.5V to VDD+0.5V VGATE ................................ VDD+0.5V *COMMENT
Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
AC OPERATING CHARACTERISTICS
Symbol Description Min. Typ. 5 tCBD Programmable 50mV Circuit Breaker delay (filter) 50 * 150 400 50 250 500 tVGD Programmable Power Good delay 1500 5* 20 80 160 tFSTSHTDN tCYC tCBRST Fast shutdown delay from Fault to VGATE off Circuit breaker cycle time CBRESET pulse width 200 OFF * tPUVF Programmable Under-Voltage filter 5 80 160 0.5 tPDD Programmable Pin Detect 5 80 * 160
* = Default value
Max.
Units s s s s s s s s ms ms ms ms ns s ns -- ms ms ms ms ms ms ms
2055 Prog Table
200 2.5
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SMH4812
Preliminary DC OPERATING CHARACTERISTICS
(Over Recommended Operating Conditions; Voltages are relative to VSS, except VGT)
Symbol VDD 5VREF ILOAD5 2.5VREF ILOAD2.5 IDD VUV VUVHYST VOV VOVHYST VGATE IGATE VSENSE ISENSE VCB Parameter Supply voltage 5V reference output 5V reference output current 2.5V reference output 2.5V reference output current Power supply current Under-Voltage threshold Under-Voltage hysteresis Over-Voltage threshold Over-Voltage hysteresis VGATE output voltage VGATE current output DRAIN SENSE threshold DRAIN SENSE current output Circuit breaker threshold Programmable Quick Trip circuit breaker threshold Off VENTS VENTSHYST VIH VIL VOL IIL VGT
(1) TA = 25C.
Conditions IDD = 3mA IDD = 3mA IDD = 3mA IDD = 3mA (1) IDD = 3mA IDD = 3mA (1) IDD = 3mA IDD = 3mA (1) IDD = 3mA
Min. 11 4.75 -1 2.475 -0.2 2.475 2.475
Typ. 12 5.00 2.500
Max. 13 5.25 1 2.525 1 10
Units V V mA V mA mA V mV V mV V A V A mV mV mV mV --
2.500 63 2.500 10
2.525 2.525 VDD
100 IDD = 3mA (1) VSENSE = VSS (1) IDD = 3mA 2.475 9 40 2.500 10 50 200 100 60 IDD = 3mA (1) IDD = 3mA 3 0 IOL = 3mA IOL = 3mA VIL = VSS 0.7 0 0 100 1.8 3.0 2.475 2.500 10 5VREF 2 0.4 0.4 2.525 2.525 11 60
VQCB
EN/TS threshold EN/TS hysteresis Input high voltage: ENPG Output low voltage: FAULT# Output low voltage: PG# Input current: PD1#, PD2#, EN/TS Gate threshold
V mV V V V V A V
2055 Elect Table
RECOMMENDED OPERATING CONDITIONS Temperature -40C to 85C.
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SMH4812
Preliminary FUNCTIONAL DESCRIPTION
GENERAL OPERATION The SMH4812 is an integrated power controller for hot swappable add-in cards. The device operates from a wide supply range and generates the signals necessary to drive an isolated output DC/DC converter. As a typical add-in board is inserted into the powered backplane physical connections must first be made with the chassis to discharge any electrostatic voltage potentials. The board then contacts the long pins on the backplane that provide power and ground. As soon as power is applied the device starts up, but does not immediately apply power to the output load. Under-voltage and over-voltage circuits inside the controller check to see that the input voltage is within a user-specified range, and pin detection signals determine whether the card is seated properly. These requirements must be met for a Pin Detect Delay period of tPDD, after which time the hot-swap controller enables VGATE to turn on the external power MOSFET switch. The VGATE output is current limited to IVGATE, allowing the slew rate to be easily modified using external passive components. During the controlled turn-on period the VDS of the MOSFET is monitored by the drain sense input. When drain sense drops below 2.5V, and VGATE gets above VDD - VGT, the power good output can begin turning on the DC/DC controller. The Power Good Enable input may be used to activate or deactivate the output load. Steady state operation is maintained as long as all conditions are normal. Any of the following events may cause the device to disable the DC/DC controller by shutting down the power MOSFET: an under-voltage or overvoltage condition on the host power supply; an overcurrent event detected on the CBSENSE input; a failure of the power MOSFET sensed via the DRAIN SENSE pin; the pin detect signals becoming invalid; the master enable (EN/TS) falling below 2.5V; the FS# input being driven low by events on the secondary side of the DC/DC controller. The SMH4812 may be configured so that after any of these events occur the VGATE output shuts off and either latches into an off state or recycles power after a cooling down period, tCYC. Powering VDD The SMH4812 contains a shunt regulator on the VDD pin that prevents the voltage from exceeding 12V. It is necessary to use a dropper resistor (RD) between the host power supply and the VDD pin in order to limit current into the device and prevent possible damage. The dropper resistor allows the device to operate across a wide range of system supply voltages, and also helps protect the device against common-mode power surges. Refer to the Applications Section for help on calculating the RD resistance value. System Enables There are several enabling inputs, which allow a host system to control the SMH4812. The Pin Detect pins (PD1# & PD2#) are two active low enables that are generally used to indicate that the add-in circuit card is properly seated. This is typically done by clamping the inputs to VSS through the implementation of an injector switch, or alternatively through the use of a staggered pins at the card-cage interface. Two shorter pins arrayed at opposite ends of the connector force the card to be fully seated (not canted) before both pin detects are enabled. Care must be taken not to exceed the maximum voltage rating of these pins during the insertion process. Refer to details in the Applications Section for proper circuit implementation. The EN/TS input provides an active high comparator input that may be used as a master enable or temperature sense input. These inputs must be held low for a period of tPDD before a power-up sequence may be initiated. Under-/Over-Voltage Sensing The Under-Voltage (UV) and Over-Voltage (OV) inputs provide a set of comparators that act in conjunction with an external resistive divider ladder to sense when the host supply voltage exceeds the user defined limits. If the input to the UV pin rises above 2.5V, or the input to the OV pin falls below 2.5V for a period of tPDD, the power-up sequence may be initiated. The tPDD filter helps prevent spurious start-up sequences while the card is being inserted. If UV falls below 2.5V or OV rises above 2.5V, the PG and VGATE outputs will be shut down immediately. Under-/Over-Voltage Filtering The SMH4812 may also be configured so that an out of tolerance condition on UV/OV will not shut off the output immediately. Instead, a filter delay may be inserted so that only sustained under-voltage or over-voltage conditions will shut off the output. When the UV/OV filter option is enabled an out of tolerance condition on UV/OV for longer than the filter delay time, tUOFLTR, activates the FAULT# output, and the VGATE and PG outputs will be latched in the off state. See Figure 1. To initiate another power-up sequence the FAULT# output must first be reset. Refer to the appropriate section on resetting the FAULT# output. The Under-/Over-Voltage Filtering feature is disabled in the default configuration of the device.
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SMH4812
Preliminary
2.5V OV / UV
CBSENSE
TCBD
50mV
TCBD
tUOFLTR
TCYC
FAULT#
VGATE
2055 Fig01
2055 Fig02
Figure 1. Under-/Over-Voltage Filter Timing
Figure 2. Circuit Breaker Cycle Mode
VDD
11 VDD 13 UV 2.5VREF OV
PD1#/ PD2#
tPDD
VDD - VGT VGATE VDD
5V DRAIN SENSE
2.5VREF
50mVREF CBSENSE PG#
2055 Fig03
Figure 3. Power On Timing Sequence
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SMH4812
Preliminary
Under-Voltage Hysteresis The Under-Voltage comparator input may be configured with a programmable level of hysteresis. The compare level may be set in steps (up to 15) of 62.5mV below 2.5V. The default under-voltage hysteresis level is set to 62.5mV. Soft Start Slew Rate Control Once all of the preconditions for powering up the DC/DC controllers have been met, the SMH4812 provides a means to soft start the external power FET. It is important to limit in-rush current to prevent damage to the add-in card or disruptions to the host power supply. For example, charging the filter capacitance (normally required at the input of the DC/DC controllers) too quickly may generate very high current. The VGATE output of the SMH4812 is current limited to IVGATE, allowing the slew rate to be easily modified using external passive components. The slew rate may be found by dividing IVGATE by the gate-to-drain capacitance placed on the external FET. A complete design example is given in the Applications Section. Load Control -- Sequencing the Secondary Supplies Once power has been ramped to the DC/DC controllers, two conditions must be met before the PG# output can be enabled: the Drain Sense voltage must be below 2.5V, and the VGATE voltage must be greater than VDD - VGT. The Drain Sense input helps ensure that the power MOSFET is not absorbing too much steady state power from operating at a high VDS. This sensor remains active at all times (except during the current regulation period). The VGATE sensor makes sure that the power MOSFET is operating well into its saturation region before allowing the loads to be switched on. Once VGATE reaches VDD - VGT this sensor is latched. When the external MOSFET is properly switched on the PG# output may be enabled (if ENPG is high). Output PG# is activated after a tPGD delay. The delay time is programmable from 50s to 160ms. The PG# output has a 12V withstand capability, so high voltages must not be connected to this pin. A bipolar transistor or an opto-isolator can be used to boost the withstand voltage to that of the host supply. See Figure 9 for connections. Forced Shutdown -- Secondary Feedback The Forced Shutdown signal (FS#) is an active low input that provides a method of receiving feedback from the secondary side of the DC/DC controllers. A built-in holdoff
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timer allows the SMH4812 to ignore the state of the FS# input until the timer period expires. The FS# input must be driven high by the end of this timer period. A low level on this input will cause a Fault condition, driving FAULT# low and shutting off the VGATE and PG# outputs. The purpose of the holdoff timer is to allow enough time for devices on the secondary side of the DC/DC controllers to power up and stabilize. This unique feature of the SMH4812 allows supervisory circuits such as an SMS44 to control the shutdown of the primary side soft start circuit, even though the secondary side initially has no power. The FS# input can be programmed to act as a second ENPG input controlling the PG# output. Circuit Breaker Operation The SMH4812 provides a number of circuit breaker functions to protect against over current conditions. A sustained over-current event could damage the host supply and/or the load circuitry. The board's load current passes through a series resistor (RS) connected between the MOSFET source (which is tied to CBSENSE) and VSS. The breaker trips whenever the voltage drop across RS is greater than 50mV for more than tCBD (a programmable filter delay ranging from 10s to 500s). Quick-TripTM Circuit Breaker Additionally, the SMH4812 provides a Quick-Trip feature that will cause the circuit breaker to trip immediately if the voltage drop across RS exceeds VQCB. The Quick-Trip level may be set to 60mV, 100mV (default), 200mV, or the feature may be disabled.
VQCB 50mV
CBSENSE
TFSTSHTDN VGATE
2055 Fig04
Figure 4. Circuit Breaker Quick Trip Response
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SMH4812
Preliminary
Current Regulation The current regulation mode is an optional feature that provides a means to regulate current through the MOSFET for a programmable period of time. See Figures 5a and 5b. If enabled the device will start the internal timer when the voltage at CBSENSE exceeds 50mV (A & G, H). Also, it attempts to limit the voltage at CBSENSE to 60mV by regulating the VGATE output (B & C vs. I). The circuit breaker will trip if the over-current condition remains after the time-out (D, E, F; & J, K, L). However, if CBSENSE drops below 50mV before the timer ends, the timer is reset and VGATE resumes normal operation. If the Quick-Trip level is exceeded then the device will bypass the current regulation timer and shut down immediately. The Current Regulation feature is disabled in the default configuration. Non-Volatile Fault Latch The SMH4812 also provides an optional nonvolatile fault latch (NVFL) circuit breaker feature. The nonvolatile fault latch essentially provides a programmable fuse on the circuit breaker. When enabled the nonvolatile fault latch will be set whenever the circuit breaker trips. Once set, it cannot be reset by cycling power.
12V
VGATE
0V 1
C F
FAULT#
0 50mV 0V
E B
CBSENSE
A
D
2055 Fig05a
Figure 5.a. Current Regulation & Shutdown
12V
VGATE
0V 1
I L
NOTE: THE
DEVICE REMAINS PERMANENTLY DISABLED
UNTIL IT IS REPROGRAMMED AT THE FACTORY.
As long as the NVFL is set, the FAULT# output will be driven active. The Non-Volatile Fault Latch feature is disabled in the default configuration. Resetting FAULT# When the circuit breaker trips the VGATE output is turned off and FAULT# is driven low. In the default condition the breaker resets automatically after a time of tCYC. In the latched condition cycling power to the board or toggling the EN/TS input will also reset the circuit breaker. If the over current condition still exists after the MOSFET switches back on, the circuit breaker will re-trip.
FAULT#
0
K H
50mV
CBSENSE
0V
G
J
2055 Fig05b
Figure 5.b. Current Regulation & Shutdown
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SMH4812
Preliminary APPLICATIONS
Operating at High Voltages The breakdown voltage of the external active and passive components limits the maximum operating voltage of the SMH4812 hot-swap controller. Components that must be able to withstand the full supply voltage are: the input and output decoupling capacitors, the protection diode in series with the DRAIN SENSE pin, the power MOSFET switch and the capacitor connected between its drain and gate, the high-voltage transistors connected to the power good outputs, and the dropper resistor connected to the controller's VDD pin. Over-Voltage and Under-Voltage Resistors In the following examples, the three resistors, R1, R2, and R3, connected to the OV and UV inputs, must be capable of withstanding the maximum supply voltage of several hundred volts. The trip voltage of the UV and OV inputs is 2.5V relative to VSS. As the input impedance of UV and OV is very high, large value resistors can be used in the resistive divider. The divider resistors should be high stability, 1% metal-film resistors to keep the under-voltage and over-voltage trip points accurate. Telecom Design Example A hot-swap telecom application may use a 48V power supply with a -25% to +50% tolerance (i.e., the 48V supply can vary from 36V to 72V). The formulae for calculating R1, R2, and R3 follow. First a peak current, IDMAX, must be specified for the resistive network. The value of the current is arbitrary, but it can't be to high (self-heating in R3 will become a problem), or too low (the value of R3 becomes very large, and R3 becomes very expensive). To set the calculations a nominal value of 250A will be assumed. With VOV (2.5V) being the over-voltage trip point, R1 is calculated by the formula:
R1 = VOV IDMAX . IDMIN = IDMAX x VSMIN . VSMAX
Substituting:
IDMIN = 250 A x 36V = 125 A . 72V
Now the value of R3 is calculated from IDMIN:
R3 = VSMIN - VUV . IDMIN
VUV is the under-voltage trip point, also 2.5V. Substituting:
R3 = 36V - 2.5V = 268k . 125 A
The closest standard 1% resistor value is 267k Then R2 is calculated:
(R1+ R2) =
or
R2 =
VUV IDMIN ,
VUV - R1. IDMIN
Substituting:
R2 = 2.5V - 10k = 20k - 10k = 10k . 125 A
Dropper Resistor Selection The SMH4812 is powered from the high-voltage supply via a dropper resistor, RD. The dropper resistor must provide the SMH4812 (and its loads) with sufficient operating current under minimum supply voltage conditions, but must not allow the maximum supply current to be exceeded under maximum supply voltage conditions. The dropper resistor value is calculated from:
Substituting:
R1 = 2.5V = 10k . 250 A
RD =
VSMIN - VDDMAX IDD + ILOAD
,
Next the minimum current that flows through the resistive divider, IDMIN, is calculated from the ratio of minimum and maximum supply voltage levels:
where VSMIN is the lowest operating supply voltage, VDDMAX is the upper limit of the SMH4812 supply voltage, IDD is minimum current required for the SMH4812 to operate, and ILOAD is any additional load current from the 2.5V and 5V outputs and between VDD and VSS.
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SMH4812
Preliminary
The min/max current limits are easily met using the dropper resistor, except in circumstances where the input voltage may swing over a very wide range (e.g., input varies between 20V and 100V). In these circumstances it may be necessary to add an 11V zener diode between VDD and VSS to handle the wide current range. The zener voltage should be below the nominal regulation voltage of the SMH4812 so that it becomes the primary regulator. MOSFET VDS(ON) Threshold The drain sense input on the SMH4812 monitors the voltage at the drain of the external power MOSFET switch with respect to VSS. When the MOSFET's VDS is below the user-defined threshold the MOSFET switch is considered to be ON. The VDS(ON)THRESHOLD is adjusted using the resistor, RT, in series with the drain sense protection diode. This protection, or blocking, diode prevents high voltage breakdown of the drain sense input when the MOSFET switch is OFF. A low leakage MMBD1401 diode offers protection up to 100V. For high voltage applications (up to 500V) the Central Semiconductor CMR1F-10M diode should be used. The VDS(ON)THRESHOLD is calculated from:
VDS (ON)THRESHOLD = VSENSE - (ISENSE x RT ) - VDIODE ,
The dropper resistor value should be chosen such that the minimum and maximum IDD and VDD specifications of the SMH4812 are maintained across the host supply's valid operating voltage range. First, subtract the minimum VDD of the SMH4812 from the low end of the voltage, and divide by the minimum IDD value. Using this value of resistance as RD find the operating current that would result from running at the high end of the supply voltage to verify that the resulting current is less than the maximum IDD current allowed. If some range of supply voltage is chosen that would cause the maximum IDD specification to be violated, then an external zener diode with a breakdown voltage of 12V should be used across VDD. As an example of choosing the proper RD value, assume the host supply voltage will range from 36 to 72V. The largest dropper resistor that can be used is: (36V-11V)/ 3mA = 8.3k. Next, confirm that this value of RD also works at the high end: (72V-13V)/8.3k = 7.08mA, which is less than 10mA. The FS# input can also be used in conjunction with a secondary-side supervisory circuit providing a positive feedback loop during the power up sequence. As an example, assume the SMH4812 is configured to turn on - 48V to a DC/DC converter with a 1.6ms delay. Further assume all of the enable inputs are true and PG# has just been sequenced on. If FS# option 4 (100BIN in register 5) has been selected, then FS# must be driven high within 1.6ms after PG# goes low, otherwise the PG output will be disabled. Ideally, there would be a secondary-side supervisor similar to the SMS44 that would have its reset timeout period programmed to be less than 1.6ms. After the supply turns on the RESET# output of the SMS44 would be released and FS# pulled high. However, if for any reason the supply doesn't turn on, the RESET# will not be released and the SMH4812 will disable the PG output.
where VDIODE is the forward voltage drop of the protection diode. The VDS(ON)THRESHOLD varies over temperature due to the temperature dependence of VDIODE and ISENSE. The calculation below gives the VDS(ON)THRESHOLD under the worst case condition of 85C ambient. Using a 68k resistor for RT gives:
VDS (ON)THRESHOLD = 2.5V - (15 A x 68k ) - 0.5V = 1V .
The voltage drop across the MOSFET switch and sense resistor, VDSS, is calculated from:
VDSS = ID (RS + RON ) ,
where ID is the MOSFET drain current, RS is the circuit breaker sense resistor and RON is the MOSFET on resistance.
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SMH4812
Preliminary APPLICATIONS CIRCUITS
0V
10nF 100V RD 6.8k
0V
2.5VREF
ENPG
VDD
EN/TS R3 UV R2
FS#
MMBTA06LT1
SMH4812
OV 10k PD1# 10k PD2#
VGATE DRAIN SENSE CBSENSE
PG# MMBD1401 47k 5VREF
FAULT#
VSS
R1 100nF 50V 100nF 1k *10 RS 20m 10nF 100V RT 68k 100nF 50V 100F 100V
MMBD1401
-48V
2055 Fig06
-48V
Figure 6. Changing Polarity of Power Good Output (PG#)
Note: Figures 6 through 9 -- the *10 resistor must be located as close as possible to the MOSFET
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SMH4812
Preliminary
0V
NTC 50k @TMAX
0V
10nF 100V
R3
RD 6.8k 1k
1M
2.5VREF
VDD
ENPG
- LMV331 50k
EN/TS
UV R2 OV 10k PD1# PD2# PG# MMBTA06LT1
SMH4812
DRAIN SENSE
10k
FS#
+
R1 100nF 50V 100nF 1k *10 RS 20m 10nF 100V RT 68k 100nF 50V 100nF 50V
VSS
VGATE
FAULT#
CBSENSE
5VREF
100k
100F 100V
MMBD1401
-48V
2055 Fig07
-48V
Figure 7. Overtemperature Shutdown
Note: Figures 6 through 9 -- the *10 resistor must be located as close as possible to the MOSFET
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2055 4.0 12/22/00
SUMMIT MICROELECTRONICS, Inc.
SMH4812
Preliminary
0V
0V
10k 10nF 100V R3 RD 6.8k
1k 1M
2.5VREF
VDD
EN1
-
EN/TS
+ EN2 - LMV 339 + EN3 - 10k + EN4 - PD1# 10k PD2# PG# UV R2
SMH4812
OV MMBTA06LT1
ENPG
DRAIN SENSE
FS#
+
R1 100nF 50V 100nF 1k *10 RS 20m 10nF 100V RT 68k 100nF 50V 100nF 50V 100F 100V
VSS
VGATE
FAULT#
CBSENSE
5VREF
100k
MMBD1401
-48V
2055 Fig08
-48V
Figure 8. Expanding Input Monitoring Capability
SUMMIT MICROELECTRONICS, Inc.
2055 4.0 12/22/00
15
SMH4812
Preliminary
0V
R3 RD 6.8k
VDD
ENPG
EN/TS
FS#
UV R2 OV 10k PD1# 10k PD2#
DRAIN SENSE
DC / DC Converter with Active Low On/Off Control +VIN +VOUT -VIN -VOUT ON/OFF
SMH4812
PG2#
MMBTA06LT1
V 0V
FAULT#
CBSENSE VGATE
5VREF 100k
R1 100nF 1k 10nF 100V 100nF 50V RS *10 10nF 100V 68k 100F 100V
VSS
100nF 50V
MMBD1401
2055 Fig09
-48V
Figure 9. Typical Application for DC/DC Converter
Note: Figures 6 through 9 -- the *10 resistor must be located as close as possible to the MOSFET
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2055 4.0 12/22/00
SUMMIT MICROELECTRONICS, Inc.
SMH4812
Preliminary PACKAGES
SSOP PACKAGE
D
JEDEC MO-137
H
1
E A
hx45
S
C
0 to 8 typ
A2 e
L
B
A1
2055 SSOP
Dimension A A1 A2 B C D E e H h L S
Inches Min. 0.061 0.004 0.055 0.008 0.0075 0.337 0.150 0.230 0.010 0.016 0.0500 Nom. 0.064 0.006 0.058 0.010 0.008 0.342 0.155 0.025BSC 0.236 0.013 0.025 0.0525 0.244 0.016 0.035 0.0550 5.84 0.25 0.41 1.27 Max. 0.068 0.0098 0.061 0.012 0.0098 0.344 0.157 Min. 1.55 0.12 1.4 0.20 0.19 8.56 3.81
Millimeters Nom. 1.63 0.15 1.47 0.25 0.20 8.69 3.94 0.635BSC 5.99 0.33 0.64 1.33 6.20 0.41 0.89 1.40
2055 SSOP Dim
Max. 1.73 0.25 1.55 0.31 0.25 8.74 3.99
SUMMIT MICROELECTRONICS, Inc.
2055 4.0 12/22/00
17
SMH4812
Preliminary
16 PIN SOIC PACKAGE
0.390 0.005 16 9 .0085 .0010 (After Plating)
0.236 0.008
0.1550.005
S
Pin 1 Index
1 OIC
6
0.151 0.005
155 0.005
1
8
0 8
0.05 BSC
0.016 0.003
DETAIL A
.016 .002 7 1 7 1 45 1 0.024 0.002
0.054 0.005 0.069 MAX .004 .007 .003 7 1 0.390 0.005 0.007 0.003 0.023 0.005 0.041
Note: 1. Reference: JEDEC publication MS-012 PTX 360-120 2. Unit: Inches 3. Mold flash, protrusion & gate burr shall not exceed 0.006 inch per side.
DETAIL A
2055 SOIC 1.0
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2055 4.0 12/22/00
SUMMIT MICROELECTRONICS, Inc.
SMH4812
Preliminary ORDERING INFORMATION
SMH4812 Base Part Number
G Package G = SSOP S = SOIC
2055 Tree 1.0
NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user's specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. This document supersedes all previous versions. (c) Copyright 2000 SUMMIT Microelectronics, Inc.
SUMMIT MICROELECTRONICS, Inc. 2055 4.0 12/22/00
19

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